Method and apparatus for serving data

ABSTRACT

VPI/VCI of an ATM cell is translated into an internal ID by distribute VPI/VCI entries into sections in a table according to a portion of each VPI/VCI entry. A section to be searched according to the portion of a VPI/VCI of the received ATM cell is selected; and a search over the selected section is performed to find an entry corresponding to the VPI/VCI of the received ATM cell. An internal ID corresponding to the found entry is outputted.

More than one reissue application has been filed for U.S. Pat. No.6,834,055. This is a continuation of application Ser. No. 12/793,729,filed Jun. 4, 2010, which is a division of application Ser. No.12/630,052, filed Dec. 3, 2009, now U.S. Pat. No. Re. 42,587, which is adivision of reissue application Ser. No. 11/642,941, filed Dec. 20,2006, now U.S. Pat. No. Re. 41,091 which is a reissue of U.S. Pat. No.6,834,055, which is a division of U.S. Pat. No. 6,208,655.

This is a divisional of U.S. patent application Ser. No. 08/979,474,filed Nov. 26, 1997, now U.S. Pat. No. 6,208,655.

The present invention relates to servers for data delivery. Traditionelservers were designed with the tendency to be actively involved in thephysical transmission of data. For applications such as video on demandor karoake on demand, deliverance of a high number of digital videostreams in real time are required. The digital video stream typicallyinclude video data compressed according to ISO/IEC 11172 or ISO/IEC13818, which are commonly known as MPEG-1 standard and MPEG-2 standardrespectively.

An ATM (Asynchronous Transfer Mode)-base server system withcapabilities, extending beyond mere data delivery has already beenproposed in the European Patent Application No. 95.200819.1.

A streaming engine for ATM communication configured as an ASIC(Application Specific Integrated Circuit) has been proposed in theinternational application WO 96/08896 published under PCT.

A method for recording and reproducing compressed video data accordingto the MEPG standard is proposed in European Patent Application EP 0 667713 A2. In this case, the compressed video data is recorded in the diskin the special form including the scan information so that the specificcompressed video data reproducing apparatus can achieve VCR functions(e.g. FF, FR).

It is an object of the present invention to improve upon the abovementioned prior art and/or to provide a server for future applications.

The present invention provides in a first aspect a method fortranslating a VPI/VCI of an ATM cell into an internal ID comprising thesteps of:

-   -   distributing VPI/VCI entries into sections in a table according        to a portion of each VPI/VCI entry;    -   receiving an ATM cell;    -   selecting a section to be searched according to the portion of a        VPI/VCI of the received ATM cell;    -   performing a search over the selected section to find an entry        corresponding to the VPI/VCI of the received ATM cell; and    -   outputting an internal ID corresponding to the found entry.

Preferred embodiment of the method according to the present inventionare described in the dependent subclaims.

Further the preseht invention provides an apparatus for translating aVPI/VCI of an ATM cell into an internal ID comprising:

-   -   a table for storing VPI/VCI entries and being divided into        sections;    -   means for distributing VPI/VCI entries into the sections in the        table according to a portion of each VPI/VCI entry;    -   means for selecting a section to be searched according to the        portion of a VPI/VCI of an received ATM cell; and    -   means for performing a search over the selected section to find        an entry corresponding to the VPI/VCI of the received ATM cell        and for outputting an internal ID corresponding to the found        entry.

The present invention provides in a second aspect an apparatus forsending data to an ATM network and receiving data from the ATM networkcomprising:

-   -   (a) a bus interface for interfacing with a bus supporting        communication between a host, a storage device and the        apparatus;    -   (b) an ATM interface for interfacing with the ATM network;    -   (c) a transmission unit for transmitting outgoing data from the        bus interface to the ATM interface, the transmission unit        including        -   (1) a first RAM interface for interfacing with RAM being            used as a buffer for buffering the outgoing data from the            bus interface,        -   (2) means for segmenting the outgoing data from the buffer            into outgoing ATM cells, and        -   (3) a traffic shaper, for controlling traffic of the            outgoing ATM cells to the ATM interface in cooperation with            the means for segmenting; and    -   (d) a reception unit for transmitting incoming data from the ATM        interface to the bus interface, the reception unit including        -   (1) means for performing VPI/VCI filtering of incoming ATM            cells,        -   (2) means for reassembling the incoming data using payload            of the incoming ATM cells, and        -   (3) a second RAM interface for interfacing RAM being used as            a buffer for buffering the incoming data the means for            reassembling.

This apparatus according to the present invention provides formanagement of running applications that interact with a large number ofclients and management modules distributed over a system, as well asmanagement of the data that are delivered. The server according to thepresent invention provides time or processing power to run higher levelmanagement tasks, as the host is less actively involved in physicaltransmission of data. The hardware according to the present invention isable to deliver data in real time under different performancerequirements and is well suited for such real time delivery. Thestreaming engine according to the present invention is able to supportsimultaneous communications with many clients and to facilitate thevideo streaming task. The server according to the present invention,also provides for interoperability, such as to serve data to any type ofclient. The content to be delivered, can be stored in a versatile form(i.e. raw or non formatted form) in the server according to the presentinvention.

The present invention provides in a third aspect a method for streamingdata from a storage device comprising the steps of:

-   -   providing write addresses for a burst data to a buffer, at least        a portion of the write addresses being non-contiguous;    -   transferring the burst data from the storage device to the        buffer via a bus supporting communication between a host, the        storage device and a streaming device;    -   writing the burst data in the buffer according to the write        addresses; and    -   reading data from the buffer in a linear fashion.

Preferred embodiment of the method according to the present inventionare described in the dependent subclaims.

Further the present invention provides a streaming device for streaminga data from a storage device comprising:

-   -   means for receiving a burst data from the storage device via a        bus supporting communication between a host, the storage device        and the streaming device;    -   means for providing write addresses for the burst data, at least        a portion of the write addresses being non-contiguous; and    -   a buffer for storing the burst data according to the write        addresses and outputting data therefrom in a linear fashion.

The present invention provides in a fourth aspect a method fordelivering data comprising the steps of:

-   -   loading at least a pair of an address and a command from a host;    -   storing the data in a buffer;    -   reading the data from the buffer according to a read pointer;    -   executing the command if a match between the address and an        address specified by the read pointer is detected; and    -   delivering the data read from the buffer after the execution of        the command.

Further the present invention provides a device for delivering datacomprising:

-   -   a command block for storing at least a pair of an address and a        command loaded from a host and detecting a match between the        address and an address specified by a read pointer of a buffer        buffering the data;    -   means for executing the command in cooperation with the command        block when the match is detected; and    -   means for delivering the data read from the buffer after the        execution of the command.

The present-invention provides in a fifth aspect a method for deliveringdata comprising the steps of:

-   -   receiving data from a network;    -   detecting at least a preset bit pattern in the data when the        received data is transmitted to a storage device;    -   adding location information corresponding to a location of the        preset bit pattern in the data to a list when the preset bit        pattern is detected;    -   storing the data in the storage device; and    -   controlling a delivery of the data from the storage device to        the network according to the location information in the list.

Preferred embodiment of this method are described in the dependentsubclaims.

Further the present invention provides an apparatus for deliveringdatacomprising:

-   -   receiving means for receiving data from a network;    -   a pattern detector for detecting at least a reset bit pattern in        the data when the data is ransmitted from the receiving means to        a storage device storing the data;    -   a list for storing location information corresponding to a        location of the preset bit pattern in the data when the preset        bit pattern is detected by the attern detector; and    -   means for controlling a delivery of the data from the storage        device to the network according to the location information in        the list.

The present invention provides in a sixth aspect a traffic shapingmethod comprising the steps of:

-   -   classifying one or more first streams into one or more classes,        each class including one or more streams having the same bit        rate characteristics;    -   setting a set of parameters to control the bit rate for each        class; and    -   executing a rate pacing of each class according to the set of        parameters.

Preferred embodiment of this method are described in the dependentsubclaims.

Further the present invention provides a traffic shaper comprising:

-   -   means for classifying one or more first streams into one or more        classes, each class including one or more streams having the        same bit rate characteristics;    -   storage means for storing a set of parameters to control the bit        rate for each class; and    -   means for executing a rate pacing of each class according to the        set of parameters in the storage means.

Further advantages, features and details of the present invention willbecome clear when reading the following description, in which referenceis made to the annexed drawings, in which:

FIG. 1 shows a general system architecture of an interactivecommunication system;

FIG. 2 shows a detail block diagram of an embodiment of the apparatusaccording to the present invention;

FIG. 3 shows a block diagram of the Tx address translator of FIG. 2;

FIG. 4 shows an example of the use of the address translator of FIG. 3;

FIGS. 5A, 5B, 5C show respective examples of address translation for TCPIP packetisation;

FIG. 6 shows an example of use of the Tx rate block of FIG. 2;

FIG. 7 shows the behaviour of a bit rate achieved by the traffic shaperof FIG. 2;

FIG. 8 shows a diagram for explaning the sending of stream within onecell period;

FIG. 9 shows the submission of cells for different classes;

FIG. 10 is a block diagram of an architecture for the traffic shaper ofFIG. 2;

FIG. 11 shows a block diagram of the command block of FIG. 2;

FIG. 12 is a diagram for explaning the operation of the byte swapper ofFIG. 2;

FIG. 13 shows a format of one ATM cell used in UNI;

FIG. 14 shows a block diagram of the VPI/VCI translator of FIG. 2;

FIG. 15 shows a block diagram of the pattern detector of FIG. 2; and

FIG. 16 shows an example of an address translator of FIG. 2.

FIG. 1 shows a general system architecture of a preferred embodiment ofan interactive communication system. This is a broad-band system thatsupports virtually any kind of interactive multi-media application.Particular attention is paid to real time multimedia delivery modeapplications.

A server 10 functions as VOD (Video On Demand) server, KOD (Karaoke OnDemand) server, and/or Internet server, etc. and communicates with STBs(Set Top Box) 18 as clients over a public network 16. The server 10consists of a local ATM switch 14 and several SMUs (Storage Medium Unit)12 that are interconnected thorough the local ATM switch 14. The mainpurposes of the local ATM switch 14 are to route data between the SMUs12 (for instance, to duplicate a movie compressed according to the MPEGstandard from one SMU to another), create a ATM-based LAN inside theserver 10, and interface to the public network 16. Each SMU 12communicates with the local ATM switch 14 at high speed, with currenttechnology at e.g. a maximum of 622 Mbps. The public network 16 isoptional and the server 10 may directly communicates with the STBs 18.

FIG. 2 shows a detail block diagram of the SMU 12. The SMU 12 hasstorage devices 20, a host 28 and a streaming engine 36 as major units.These units are interconnected via a PCI (Peripheral ComponentInterconnect) bus 24. A host CPU 30 and a host memory 32 in the host 28are connected via MIPS bus 34 in a conventional configuration. In thisembodiment the MIPS bus 34 is connected to the PCI bus 24 thorough a PCIbridge 26. The host 28 is primarily intended for running applicationslike VOD, KOD, internet server that interact with clients or STBs.

The storage devices 20 contains one or more strings of hard disks. Thesehard disks are connected via SCSI or Fibre Channel and store real timesensitive data like MPEG-2 encoded video streams and the contents ofdata packets like the body of TCP/IP (Transmission ControlProtocol/Internet Protocol) packets without the headers.

The streaming engine 36 is preferably configured as a single ASIC(Application Specific IntegratedCircuit). The streaming engine 36streams the real time sensitive data and the data packets. The streamingengine 36 has a transmission path 50 and a reception path 80 as majorparts and a PCI interface 38 and an interface 40. The transmission path50 handles the outgoing data stream from the storage devices 20 and thehost 28 to the local ATM switch 14. The reception path 80 handles theincoming data stream from the local ATM switch 14 to the storage devices20 and the host 28. The high speed connections and the independence ofthe transmission path and reception path allow for 622 Mbpssimultaneously in both directions.

The PCI interface 38 interfaces the PCI bus 24 with the transmissionpath 50 and the reception path 80. The PCI interface 38 transfers theoutgoing data stream from the PCI bus 24 to a PCI FIFO 52 in thetransmission path 50 and transfers the incoming data stream from a PCIFIFO 98 in the reception path to the PCI bus 24.

The interface 40 interfaces the transmission path 50 and the receptionpath 80 with an external physical layer device (not shown) connected tothe local ATM switch 14. The interface 40 can include two types of ATMinterfaces according to the UTOPIA (Universal Test and Operation PHYInterface for ATM) level 2 standard. One is UTOPIA interface in 8 bitwide data path mode and the other is UTOPIA interface in 16 bit widedata path mode.

The transmission path 50 consist of several functional blocks which acttogether to perform high speed transmission.

The first block in the transmission path 50 is the Tx address translator54, which places the outgoing data stream from the PCI FIFO 52 intohost-specified memory locations of a stream buffer 44 allocated in anexternal RAM 42. This allows for controlled “scattering” of data intonon-contiguous memory, which is useful for an operation which to someextent resembles so-called RAID (Redundant Array of Inexpensive Disks)operation which ensures integrity of data streams and TCP/IPpacketisation.

The TCP/IP checksum block 56 provides hardware support for calculatingTCP/IP checksums. Its function is to calculate and maintain a partialchecksum for each packet until all data has been transferred. The TCP/IPchecksum block 56 works together with the Tx address translator 54 tocreate TCP/IP packets directly in the stream buffer 44. The TCP/IPheader and payload of the packets are placed in the stream buffer 44separately, passing through the checksum block 56 which keeps a partialchecksum. As soon as all data is in the stream buffer 44, the checksumvalue is placed in the correct position of TCP/IP header, the packet isready for transmission,

The RAM interface 58 forms an interface between the external RAM 42 andthe transmission path 50. The external RAM 42 may comprise dual portedSDRAM (Synchronous Dynamic RAM). This external RAM 42 includes severalstream buffers 44 to decouple the bursty data traffic from the disks ofthe storage devices 20 and provides the required constant bit rate datastreams to the ATM-network 16. Each stream buffer handles one outgoingdata stream. In the contrast to the incoming direction, since the dataflow characteristics in the outgoing direction are fully predictable(controllable), the buffer requirements can be estimated beforehand.Therefore the stream buffers 44 are statically allocated in the externalRAM 42.

The Tx RAID or SDI (Stream Data Integrity) block 60 provides support fordata redundancy. The Tx address translator 54 places the data as neededin stream buffer 44. Then, as data is output from the stream buffer 44,the Tx RAID block 60 corrects error data in the event that one of thedisks in the storage devices 20 breaks down.

The traffic shaper 62 controls the streaming of the outgoing data fromthe stream buffers 44 to the ATM network 16. It is designed for veryaccurate rate pacing and low CDV (Cell Delay Variation). The trafficshaper 62 consists of two main sections. One section handles highpriority data such as video traffic, and the other section handlesgeneral data traffic of low priority.

The command block 66 is intended to off-load the host especially 28 ofreal-time sensitive jobs. It performs actions triggered by thetransmission of the content of exact known locations in the outgoingdata stream.

The segmentation block 70 segments the outgoing data stream providedfrom the stream buffer 44 into AAL-5 PDUs (ATM Adaptation Layer-5Protocol Data Units), and maps the AAL-5 PDUs into ATM cells. In casethe outgoing data stream is MPEG-2 SPTS (Single Program TransportStream), the segmentation block 70 is able to segment two TS packets inthe MPEG-2 SPTS to one AAL-5 PDU, unless there are less than two TSpackets left in the MPEG-2 SPTS, in the latter case the AAL-5 PDU mapsinto eight ATM cells. In the general case, the AAL-5 segmentation iscontrolled by the PDU size which is programmable per stream.

The reception path 80 has several blocks corresponding to the reverseoperation of the blocks of transmission path 50.

A VPI/VCI (Virtual Path Identifier/Virtual Channel Identifier) filteringblock 84 performs fast and efficient VPI/VCI filtering of the incomingATM cells. This is done by a combined hash and linear search functionsover the entries in a VPI/VCI table.

A reassembly block 86 basically performs the inverse functions of thesegmentation block 70. The reassembly block 86 reconstructs the AAL-5PDUs using payload of the ATM cells, then maps the AAL-5 PDUs into theupper layer data (e.g., MPEG-2 SPTS, TCP/IP Packets).

A TCP checksum verification block 88 verifies the TCP checksum in theTCP header if the incoming data stream is transmitted via TCP.

A pattern detector 92 allows a limited number of bit patterns to bedetected in an incoming data stream. A list is created, indicatingexactly where the specified bit patterns occur in the stream. Thissupports certain processing tasks that can be performed on-the-fly,whereas they would otherwise have to be done with post-processing.

A Rx RAID or SDI block 90 adds redundancy to the incoming data stream.If a sequence of N words is written to a buffer (not shown), the parityover these N words is written next. This function can be turned on/off.If the incoming data stream will be stored in the storage device 20 andtransmitted later as TCP/IP packets via the transmission path 50, thefunction is turned off.

A RAM interface 94 is an interface between the reception path 80 and anexternal RAM 46. The external RAM 46 may comprise dual ported SDRAM. Theexternal RAM 46 is used as several stream buffers 48 storing incomingdata streams. Each stream buffer 48 handles one incoming data stream.Incoming data streams can have unpredictable properties. For instance,some of data packets can be very bursty. This means the required buffercapacity varies from stream to stream and from time to time. Therefore,In the external RAM 46, a dynamic buffer allocation is preferred.

A Rx address translator 96 provides appropriate read addresses to thestream buffer 48.

The details of the major blocks in the streaming engine 36 are describedbelow.

Tx Address Translator

The outgoing data stream is provided from the storage device 20 to thestreaming engine 36 in burst transmission over the PCI bus 24. Thepurpose of the Tx address translator 54 is to scatter one contiguous DMAburst in appropriate areas of the stream buffer 44.

FIG. 3 shows a block diagram of the Tx address translator 54. Before onecontiguous DMA burst from the storage device 20 arrives, the correctstarting address is written to a register 102 via a storage devicecontroller 22. The content of the register 102 is used as write addressfor the stream buffer 44. A counter 106 counts the number of bits of theoutgoing data stream from the PCI FIFO 52. Each time a data wordconsisting of 32 bits passes the counter 106, it inform a incrementcontroller 104 that a word is transferred to the stream buffer 44. Witheach new word, the increment controller 104 increments the content ofthe register 102 with ADDRESS_INCREMENT, which is a programmable value.In case of the outgoing data stream being RAID processed data, the valueof ADDRESS_INCREMENT is basically set according to the number of disksused for RAID system. In case of the outgoing data stream being payloadof a TCP/IP packet, the value of ADDRESS INCREMENT is basically setaccording to packetisation parameters.

An address translation when the outgoing data stream is RAID processeddata, is described below with reference to FIG. 4. In this example, theRAID or SDI system consists of four disks Disk 0, Disk 1, Disk 2 andDisk 3. The Disk 0 contains words 1, 4, 7, to be transmitted to thelocal ATM switch 14. The Disk 1 also contains words 2, 5, 8 . . . to betransmitted to the local ATM switch 14. The Disk 2 also contains words3, 6, 9 . . . to be transmitted to the local ATM switch 14. The Disk 3contains parity words 0, 1, 2 . . . for error correction. Each parityword (e.g., parity 0) has been generated in the Rx RAID block 90 fromthree words (e.g., words 1, 2 and 3) which constitute so-called stripeunit of RAID together with the parity word.

In the event of failure in one of the disks (e.g., Disk 2), onecontiguous DMA burst including parity words is transferred to the Txaddress translator 54. For ease of explanation, assume that the size ofone contiguous DMA burst is 96 bytes (24 words), although the actualsize can be larger than 100 k bytes (depending on the speed of the hard-and/or software). In this case, the contiguous DMA burst 120 consists ofwords 1, 4, 7, 10, 13, 16 from the Disk 0, words 2, 5, 8, 11, 14, 17from the Disk 1, words 3, 6, 9, 12, 15, 18 from the Disk 2, and paritywords 0, 1, 2, 3, 4, 5 from the Disk 3. The Tx address translator 54generates the following sequence of addresses:

178, 182, 186, 190, 194, 198 (data from Disk 0)

179, 183, 187, 191, 195, 199 (data from Disk 1)

180, 184, 188, 192, 196, 200 (data from Disk 2)

181, 185, 189, 193, 197, 204 (data from Disk 3)

More specifically, before the contiguous DMA burst 120 arrives at thestream buffer 44, a value 178 is stored in the register 102 as thestarting address. Then the word 1 form Disk 0 is written in the address178 in the stream buffer 44. When the word 1 passes the counter 106, theincrement controller 104 increments the value 178 in the register 102with ADDRESS_INCREMENT of a value corresponding to the number of disks.Then the word 4 from the Disk 0 is written in the address 182 in thestream buffer 44. When the word 4 passes the counter 106, the incrementcontroller 104 increments the value 182 in the register 102 withADDRESS_INCREMENT of a value 4. Then the word 7 from the Disk 0 iswritten in the address 186 in the stream buffer 44. Similarly, remainingwords 10, 13 and 16 from Disk 0 are written in the addresses 190, 194,198 which are the number of disks apart in the stream buffer 44.

When the word 16 from Disk 0 passes the counter 106, the incrementcontroller 104 increments the value 198 in the register 102 withADDRESS_INCREMENT of a value −19. Then the word 2 from Disk 1 is writtenin the address 179 in the stream buffer 44. When the word 2 passes thecounter 106, the increment controller 104 increments the value 179 inthe register 102 with ADDRESS_INCREMENT of a value 4. Then the word 5from Disk 1 is written in the address 183 in the stream buffer 44. Whenthe word 5 passes the counter 106, the increment controller 104increments the value 183 in the register 102 with ADDRESS_INCREMENT of avalue 4. Then the word 8 from Disk 1 is written in the address 187 inthe stream buffer 44. Similarly, remaining words from Disk 1 are writtenin the addresses 191, 195, 199 which are the number of disks apart instream buffer 44.

In the same way, words from the Disks 2 and 3 are written in appropriateaddresses in the stream buffer 44; The words written in the streambuffer 44 are read in liner fashion and provided to the Tx RAID block 60to correct errors.

When the outgoing data stream from the storage device 20 is TCP/IPpayload, the address translator 54 and the TCP checksum calculationblock 56 work closely together to provide support for TCP/IP packetgeneration. The host 28 pre-programs the Tx address translator 54 sothat data is distributed according to a specified packet size. At firstthe host 28 needs to know all the packetisation parameters. Importantparameters for this operation are TCP payload size, TCP header size, IPheader size and IP payload size. TCP header and IP header basically havespace for optional data but this is in practice not used. Therefore, asimplification can be introduced by assuming default sizes for theheaders: TCP header size is 5 words (20 bytes) and IP header size is 5words (20 bytes).

The mechanism can be described as follows.

The host 28 itself does a partial checksum calculation over thepseudo-header of the TCP/IP header. Then it initializes a TCP checksumregister 57 in the TCP checksum block 56 for that TCP/IP packet withthis value. Space for the stream buffer 44 also will be reserved in theexternal RAM 42 to fit the full TCP packet plus the TCP and IP headeroverhead.

The host 28 will then instruct the increment controller 104 in the Txaddress translator 54 with the TCP payload size, TCP header size, IPheader size and IP payload size. The TCP payload can then be sent as onecontiguous DMA burst over the PCI bus 24 and placed into the area in thestream buffer 44 reserved for it by the Tx address translator 54,leaving space for the headers. As it goes from the PCI bus 24 to thestream buffer 44, the checksum calculation block 56 updates the partialchecksum in the TCP checksum register 57. Note that with this method thepayload, representing usually the bulk of the TCP/IP packets, does notneed to be copied first from the storage devices 20 to the host memory32 for processing it and then to the stream buffer 44. This savesvaluable bus bandwidth and overhead for the host CPU 30. After thepayload has been written, the header information, prepared by the host28, is sent to the stream buffer 44 via the address translator 54. Aswith the payload, the Tx address translator 54 places the header in thepreviously reserved memory locations.

This sequence can be reversed, whereby the header information is writtenfirst and the payload second.

In either case, when both the header and the payload have been written,the TCP checksum will be complete and can be copied to the correctlocation automatically.

This mechanism can also be used to efficiently support segmenting of aTCP packet into multiple smaller IP packets. In this case, space isreserved for each IP packet. The TCP packet data (header+payload) issegmented into these packets and the header of each IP packet is writtenby the host 28.

All IP packets will be the same size except for the last block, which islikely to have a different size than the others. The address translator54 takes this in to account. After the complete TCP/IP packet(s) hasbeen formed, it is ready for transmission.

FIGS. 5A, 5B and 5C shows an example of address translation for TCP/IPpacketisation. In this case, before the TCP/IP payload sent as onecontiguous DMA burst 130 arrives at the stream buffer 44, a value 310 isstored in the register 102 as the starting write address, then the firstword of the first data is written in the address 310 in the streambuffer 44. When the first word of the first data passes the counter 106,the increment controller 104 increments the value 310 in the register102 with ADDRESS_INCREMENT of value 1. Then the second word of the firstdata is written in the address 311 in the stream buffer 44. When thesecond word of the first data passes the counter 106, the incrementcontroller 104 increments the value 311 in the register 102 withADDRESS_INCREMENT of value 1. Then the third word of the first data iswritten in the address 312 in the stream buffer 44. The increment withADDRESS_INCREMENT of value 1 is repeated a number of times correspondingto the IP payload size. Thus the first data of the TCP/IP payload iswritten in an appropriate area.

Then the increment controller 104 increments the content in the register102 with ADDRESS INCREMENT of a value corresponding to IP header size.Then the writing of second data starts from the address according to thecontent of the register 102. Thus the address translator 54 generateswrite addresses for the payload so that the space for the headers areleft. The last data is likely to have a different size than the others.The size of the last data is calculated in the increment controller 104by the following expression:

The last data size=TCP payload size mod IP payload size

Therefore the number of increment is controlled taking the last datasize into account. In this way, the payload sent as one contiguous DMAburst is scattered in the shaded areas in the stream buffer 44 shown asFIG. 5A.

Next, When the TCP header 132 is sent as one contiguous burst over thePCI bus 24, the address translator 54 generates write addressescorresponding to the previously reserved memory locations for the TCPheader in the stream buffer 44.

More specifically, before the TCP header sent as one contiguous burst132 arrives at the stream buffer 44, a value 305 is set in the register102 as the starting write address, whereafter the first word of the TCPheader is written in the address 305 in the stream buffer 44. When thefirst word of the TCP header passes the counter 106, the incrementcontroller 104 increments the value 305 in the register 102 withADDRESS_INCREMENT of value 1. Then the second word of the TCP header iswritten in the address 306 in the stream buffer 44. When the second wordof the TCP header passes the counter 106, the increment controller 104increments the value 306 in the register 102 with ADDRESS_INCREMENT ofvalue 1. Then the third word of the TCP header is written in the address307 in the stream buffer 44. The increment with ADDRESS INCREMENT ofvalue 1 is repeated a number of times corresponding to the TCP headersize. Thus the TCP header is written in the shaded area in the streambuffer 44 shown as FIG. 5B.

Next, When the IP headers 134 are sent as one contiguous burst over thePCI bus 24, the address translator 54 generates write addressescorresponding to the previously reserved memory locations for the IPheaders in the stream buffer 44.

More specifically, before the IP headers sent as one contiguous burst134 arrives at the stream buffer 44, a value 300 is set in the register102 as the starting write address, whereafter the first word of thefirst IP header is written in the address 300 in the stream buffer 44.When the first word of the first IP header passes the counter 106, theincrement controller 104 increments the value 300 in the register 102with ADDRESS_INCREMENT of value 1. Then the second word of the first IPheader is written in the address 301 in the stream buffer 44. When thesecond word of the first IP header passes the counter 106, the incrementcontroller 104 increments the value 301 in the register 102 withADDRESS_INCREMENT of value 1. Then the third word of the first IP headeris written in the address 302 in the stream buffer 44. The incrementwith ADDRESS_INCREMENT of value 1 is repeated a number of timescorresponding to the IP header size.

Then the increment controller 104 increments the content in the register102 with ADDRESS_INCREMENT of a value corresponding to TCP headersize+IP payload size. Then the writing of second IP header starts fromthe address according to the content of the register 102. Thus the IPheaders are written in the shaded areas in the stream buffer 44 shown asFIG. 5C.

Next, the TCP checksum completed by the TCP checksum block 56 is copiedto the correct location.

In this way, the TCP/IP packetisation is completed and can be read fromthe stream buffer 44 in linear fashion.

In the above embodiment, TCP/IP packetisation is mentioned. However itis possible to use UDP (User Datagram Protocol) instead of TCP. In thiscase, the default size of UDP header is 2 words (8 bytes).

In addition, in the above embodiment, the TCP header and the IP headersare sent as different bursts from the host 28 to the Tx addresstranslator 54. However it is possible to send the TCP header and the IPheaders together as one contiguous burst from the host 28 to the Txaddress translator 54.

Tx RAID or SDI block

In the sequence of words in the stream buffer 44, parity words may beinserted. This redundancy provides a means for correcting errors. The TxRAID or SDI block 60 takes in a sequence of N+1 words of which the lastword is the parity over the N first words. In case it is indicated byhardware and/or software, that word M is corrupt, e.g., because of adisk failure, the parity word is retrieved from the storage device 20and used to reconstruct the word M.

For example, in case of FIG. 4, the words 3, 6, 9, 12, 15, 18 from thefailure Disk 2 in the input data 142 include error shown as FIG. 6. TheTx RAID block 60 reconstruct the word 3 using the words 1, 2 and theparity word 0. The Tx RAID block 60 reconstruct the word 6 using thewords 4, 5 and the parity word 1. Similarly, the words 9, 12, 15, 18 arereconstructed by the Tx RAID block 60. Thus the Tx RAID block 60performs error correction and outputs the sequence 142 of the words 1,2, 3, 4. . . without errors.

The RAID function can be turned on/off by the command block 66.

Traffic Shaper

The traffic shaper 62 consists of two main sections one section handleshigh priority data such as video traffic, and a low priority sectionhandles general data traffic.

The high priority section is organized into several traffic classes, inwhich a class is a group of one or more streams having the same bit ratecharacteristic. For example, all streams of a CBR (Constant Bit Rate) at2 Mbps belong to the same class. A class of VBR (Variable Bit Rate) typetypically contains only one stream, because it is unlikely that two VBRstreams have identical bandwidth patterns at all times. Each class has asingle set of transmission parameters for controlling the bit rate,providing for low CDV (Cell Delay Variation) and accurate rate pacing.The number of classes is programmable but limited to maximum 128.

Each class has two main transmission parameters, an ideal scheduled time(TS) and an increment (A) for the Ts. The basic mechanism is that whenTS becomes equal to or less than a reference clock, a stream pointer isput into the transmit queue. At the same time the value TS isincremented with the value Δ. The ransmit queue is a first in first outqueue that will submit the stream indicated by the stream pointer theATM fifo 72 as soon as possible.

In the high priority section a high accuracy bit rate and low CDV areachieved following mechanisms.

Due to the finite resolution of the reference clock, having a single Δvalue usually does not give the desired accuracy. To achieve the desiredaccuracy, two Δ values are used alternatively that are just one countervalue apart. These two values result in a rate that is slightly aboveand below the required bit rate. Using each Δ value for differentnumbers of cells compensates for the limited clock resolution and canprovide arbitrary accuracy. Δ_(H) and Δ_(L) (where Δ_(L)=Δ_(H)+1)represent the two different increment values. The N_(H) and N_(L)parameters represent the number of cells for which the correspondingincrement value are alternatively valid. By means of this mechanism, thestream is modulated whereby the average bit rate approaches the requiredbit rate within the desired accuracy. FIG. 7 shows a behavior of a bitrate achieved by this mechanism. In FIG. 7, N_(H) cells are sent atΔ_(H) and N_(L) cells are sent at Δ_(l). This sequence is repeatedcyclically. Thus the average bit rate shown by a dotted line ismaintained as a long term bit rate.

Low CDV is achieved by reducing the collisions in scheduling times ofcells from different streams. A major cause of collisions in manyexisting traffic shaping mechanisms is that streams of the same bit rateare scheduled at the same time. This is particularly a problem whenthere is a large number of streams and a low number of independent bitrates. This problem is addressed in the preferred embodiment by evenlyspacing the cells of streams belonging to the same class. In otherwords, if the increment for one stream should be Δ, the increment forthe class is Δ/n, where n is the number of streams in a class. Everytime a class is to be serviced, the data is taken from successivestreams. For example, If cells of the stream 0 belonging to Class 0should be incremented by Δ, each cell of the streams (i.e. stream0−stream n−1) belonging to the same class 0 is sent with the space ofΔ/n shown as FIG. 8.

By the combination of the above two mechanisms, a high accuracy bit rateand low CDV are achieved. If the transmit queue does not get blocked,the cells are submitted shown as FIG. 9.

The high priority section also handles VBR traffic. The traffic shaper62 supports smooth update of the transmission parameters. This updatecan be done by the host 28 but also by the command block 66. The commandblock 66 is programmed by the host 28, and its actions are triggeredwhen an exact location is transmitted from the stream buffer 44. Onesuch action is to replace the transmission parameters for a specifiedstream in the traffic shaper 62. As soon as the data just before achange in bit rate are sent, the command block 66 updates theparameters. Once it is set-up, this process is autonomous and does notrequire interaction of the host CPU 30 anymore. As a consequence, thehost 28 does not need to interact exactly at the moment interactionwould be required. In this way the real-time character of the stream ismaintained and the host load kept to a minimum.

The low priority section is organized into e.g. fixed 32 trafficclasses, in which a class is a group of one or more streams having thesame PCR (Peak Cell Rate). In terms of the general data traffic, thereal-time constraints are much less significant. The main objective ofthe traffic shaping of the low priority section is to limit the PCR inorder to avoid network policing. The traffic shaping of the data packetsis implemented by a mechanism using an ideal scheduled time (TS) and anincrement (Δ) for the TS, which is similar to the basic traffic shapingmechanism in the high priority section. However, scheduling of datapackets gets a lower priority than real time traffic. Only if thetransmit queue of the high priority section is empty, a stream of thedata packets can be submitted to the ATM FIFO 72.

The mechanism is implemented with an architecture shown as FIG. 10. Thetraffic shaper 62 consists of the high priority section 200 and the lowpriority section 202 as mentioned above.

In the high priority section 200, a memory 203 stores a set of newtransmission parameters for each class provided from the host 28. Eachset of the new transmission parameters consists of TS_(i), Δ_(H)i,Δ_(L)i, N_(H)i, N_(L)i and Pt_(i) (where 0<i<127). In this embodimentPt_(i) contains one or more stream pointers which indicate one or morestreams attached to the class i. A memory 206 stores currenttransmission-parameters. When a command is instructed by the host 28 orthe command block 66, an update logic 204 is triggered by the command,whereby the current transmission parameters in the memory 206 areupdated with the new transmission parameters in the memory 203. Aregister 212 stores a parameter Nr_Classes indicating the number ofclass from the host 28 at receipt thereof. A traffic logic 208 checksfor each of classes from 0 to Nr_Classes-1 whether TS_(i) is equal to orless than the current time indicated by a reference clock 210. If so,the stream pointer of the first stream attached to this class i isinserted to a high priority transmit queue 216 and TS_(i) in the memory206 is incremented with Δ_(H)i or Δ_(L)i of this class i by the trafficlogic 208. The Δ_(H)i and Δ_(L)i are alternated according to the N_(H)iand N_(L)i. Then the segmentation block 70 receives the stream pointerfrom the high priority transmit queue 216 and puts a ATM cell belongingto the stream indicated by the stream pointer into ATM FIFO 72.

In the low priority section 202, a memory 218 stores a set oftransmission parameters for each class provided from the host 28. Inthis embodiment each set of the transmission parameters consists ofTS_(j), Δ_(j) and Pt_(j) (where 0<j<31). Pt_(j) contains one or morestream pointers which indicate one or more streams attached to the classj. A traffic logic 220 checks each of classes from 0 to 31 if TS_(j) isequal to or less than the current time indicated by the reference clock210 and monitors where the high priority transmit queue 216 is empty. Ifso, the stream pointer of the first stream attached to this class j isinserted to a low priority transmit queue 222 and TS_(j) in the memory218 is incremented with Δ_(j) of this class j by the traffic logic 220.Then the segmentation block 70 receives the stream pointer from the lowpriority transmit queue 222 and puts a ATM cell belonging to the streamindicated by the stream pointer into ATM FIFO 72.

In the above embodiment, a traffic shaping mechanism being similar tothe mechanism of high priority section 200 is applied to the lowpriority section 202. However conventional leaky bucket mechanism may beapplied to the traffic shaping mechanism of the low priority section202.

Command Block

Real time data delivery may sometimes involve actions occurring atspecific locations in the outgoing data stream. These actions must beimmediate in order to maintain the integrity of the stream. Due to themany responsibilities of the host 28, timely interaction cannot alwaysguaranteed. In the preferred embodiment, it is the responsibility of thecommand block 66 to perform these interactions. In principle, the host28 knows exactly where in the outgoing data stream the streamingparameters need to be adjusted. Since each stream buffer 44 is allocatedstatically as mentioned above, it is possible to express a location,where the actions should be taken, in read pointer of the stream buffer44. The host 28 loads a list of the command block 66 with a number ofinstructions at the appropriate moment in time. The appropriate time isthe time between the loading of the outgoing data stream to the streambuffer 44 and the time that the outgoing data stream is sent out fromthe stream buffer 44. The command block 66 scans the read pointer of thestream buffer 44. If a match with a specified address is found, acommand that is linked to that address will be executed and the commandwill be purged from the command block 66.

The command block 66 triggers on the address of the data leaving thestream buffer 44. When reading a stream buffer 44, the read pointer isgradually incremented with a wrap-around. Each stream has a linked listthat contain the (address, command) pairs to be stored according to theaddress. An address is a pair (L, M) indicating the address in the fileand is independent from the physical address. L is the number of blocks,with a block size equal to the size of the stream buffer 44. M issequence number in the last block. Each stream maintains a WAC(Wrap-around counter) that counts the number of times the read pointerhas been wrapped around.

An address match is found if

L=WAC and M=Read Pointer−Buffer Offset

This mechanism is implemented as follows. FIG. 11 shows a block diagramof the command block 66. The command block 66 consists of severalcommand generators 300. Each command generator 300 handles the commandsfor each outgoing data stream. The host 28 loads a list of commands inthe command register 316 in each command generator 300 at theappropriate moment in time.

In a command generator 300, a register 302 stores the Buffer Offset. Acomparator 304 compares the Buffer Offset in the register 302 with theread pointer of the stream buffer 44. When a wrap-around occurs, theread pointer takes the Buffer Offset. Therefore when the match isdetected by the comparator 304, the WAC (Wrap-Around Counter) 306 isincremented. The comparator 308 compares the count of the WAC 306 withcurrent L provided from the command register 316. A comparator 310compares current M provided from the command register 316 with the readpointer - Buffer Offset. When the matches are detected by the comparator308 and the comparator 310, the AND gate 312 dequeues a current commandstored by a queue 314. Each time a current command corresponding to acurrent address (L, M) is output from the queue 314, a commandcorresponding to a next address is queued in the queue 314 from thecommand register 316. Thus each command generator 300 instructs commandsaccording to a read pointer of the stream buffer 44.

The commands to be instructed from the command block 66 are:

Change bit rate: This command will allow to change a stream bandwidth.When this command is instructed, the traffic shaper 62 detach a streamfrom its current class, updates the Δ values for the current class,attach the stream to a new class and update the linked Δ values of thenew class. Thus the bit rate of individual steams is changed at specificstream locations. This is useful for MPEG bit stream of VBR (variablebit rate), for example.Insert RCI: This command allows to insert an RCI (Rate change Indicator)at specific location in the stream. The RCI is able to notify thedistant terminal (e.g., STB 18) the rate changes at that moment and aidsclock recovery for MPEG decoders. The detail of the RCI is described as“data rate data” in the European Patent Application EP 0 712 250 A2.When this command is instructed, the RCI generator 68 generates the RCIand the segmentation block 70 terminates the current segmentation and aseparate AAL-5 PDU (one ATM cell) for the RCI is generated. This isuseful for MPEG bit stream of VBR.Enable RAID: This command set the appropriate parameters in the Tx RAIDblock 60 for the error correction.Disable RAID: This function is the inverse of the above Enable RAID.Perform Byte Swap: This command allows to cope with little endian/bigendian problems between the server 10 and the STB 18. When this commandis instructed, the byte swapper 64 reorders the bytes within a word 350in the outgoing stream in an order of a word 352 shown as FIG. 12.Enable different PDU-Size: TCP can require segmentation. One TCP packetis to be divided in different IP-packets. The last IP packet requiresusually a different AAL-5 PDU size than the previous one. When thiscommand is instructed, the segmentation block 70 change the AAL-5 PDUsize.Interrupt CPU: This is the most general function. It requests the hostCPU 30 interaction upon detection of a certain location in the stream.VPI/VCI Filtering Block

FIG. 13 shows a format of one ATM cell used in UNI (User NetworkInterface). One ATM cell consists of 53 bytes. First 5 bytes constitutea ATM header and the remaining 48 bytes carry payload. The first 4 bitsin the ATM header is called GFC (Generic Flow Control). The following 24bits in the ATM header is called VPI/VCI. Actually, the VPI/VCI consistsof VPI of 8 bits and VCI of 16 bits. The following 3 bits in the ATMheader is called PT (Payload Type). The following 1 bit in the ATMheader is called CLP (Cell Loss Priority). The last 8 bits in the ATMheader is called HEC (Header Error Control). The VPI/VCI filtering block84 receives such ATM cells from ATM FIFO 82.

The VPI/VCI filtering block 84 determines whether a VPI/VCI of thereceived ATM cell is an element of the set of VPI/VCIs that should beaccepted, determines to which stream the ATM cell belongs, and filtersOAM (Operation, Administration and Maintenance) F5 cells. To achievethis filtering process, a VPI/VCI translation from a VPI/VCI to aninternal stream ID is performed in a VPI/VCI translator 85 in theVPI/VCI filtering block 84.

The object of the VPI/VCI translation mechanism is to allow as wide arange of legal VPI/VCIs as possible, while at the same time facilitatingfast translation. Preferably, all VPI/VCIs should be admissable. TheVPI/VCI translation can be done using conventional binary searchtechniques. However, due to time constraints, the largest acceptablesearch is of the order of a binary search of 512 entries. On the otherhand, the maximum number of active VPI/VCIs should be greater than 512to support simultaneous communications with a large number of clients.

In order to meet the object, the VPI/VCI table is divided up intosections of 512 entries. Each entry indicates a relation between aVPI/VCI and an internal stream ID is entered into a certain sectiondepending on a distribution mechanism and within each section theentries are ordered.

Upon reception of a ATM cell, once the correct section has been found, abinary search can be performed over that section to find the correctentry. Therefore the distribution mechanism to distribute the VPI/VCIsmust allow immediate indexing into a section according to the VPI/VCI.Moreover, to allow for efficient use of the VPI/VCI table, the mechanismmust allow for a wide distribution of the VPI/VCIs. In other words, themechanism must distribute the entries as randomly as possible over theentire VPI/VCI table. If a VPI/VCI maps into a section of the VPI/VCItable that is already full, it must be rejected even though there may bespace in other sections.

One distribution mechanism that fits to the requirements is to simplyuse the lower X (where X is integer; e.g., 3) bits of the VCI as hashkey to index into the VPI/VCI table. It is reasonable that when thereare a large number of active VP/VCs the lower bits will be the mostrandom of the 24 bits VPI/VCI field and allow for an even distribution.

Using this type of mechanism, the requirements of fast look up and noillegal or inadmissable VPI/VCIs are met. The mechanism is implementedas follows.

FIG. 14 shows a block diagram of the VPI/VCI translator 85. When a newVP/VC become active, a new entry indicating a VPI/VCI of that new VP/VCand an internal stream ID corresponding to that VPI/VCI is entered intoa section according to the lower 3 bits of the VCI (i.e., bits 7, 6, 5of 4-th byte in FIG. 13) via a hash function 400. More specifically, ifthe lower 3 bits of the VCI is 0.000, the entry is stored in the section1 in the VPI/VCI table 402. If the lower 3 bits of the VCI is 001, theentry is stored in the section 2 in the VPI/VCI table 402. If the lower3 bits of the VCI is 010, the entry is stored in the section 3 in theVPI/VCI table 402. Similarly, all new entries are stored in appropriatesections according to the lower 3 bits of the VCI. Thus, the VPI/VCItable 402 of e.g. 4096 entries is divided up into 8 sections (section1-8) of e.g. 512 entries. Within each section the entries are reorderedin an ascending or descending order to implement a binary search.

Upon reception of an ATM cell, the VPI/VCI of the received ATM cell isprovided to a search engine 420 and the hash function 400. The hashfunction 400 provides a section index based on the lower 3 bits of theVPI/VCI to the search engine 420. Then a binary search is performed bythe search engine 420 over a section corresponding to the section indexto find the correct entry. For example, if the lower 3 bits of the VCIof the received ATM cell is 010, the hash function 400 provides 3 as thesection index to the search engine 420. Then, the search engine 420performs a binary search over the section 3 to find a correct entry andoutputs a internal stream ID of the found entry. If the lower 3 bits ofthe VCI of the received ATM cell is 111, the hash function 400 provides8 as the section index to the search engine 420. Then, the search engine420 performs a binary search over the section 8 to find a correct entryand outputs a internal stream ID of the found entry. The output internalstream ID is used for the filtering process.

In the above embodiment, the lower 3 bits of the VPI/VCI field is simplyused as a section index. However, a more complex hash function may beused over the VPI/VCI field to generate a section index.

In the above embodiment, when a new VP/VC becomes active, the new entryis entered to an appropriate section via the hash function 400. However,it is possible to create a new VPI/VCI table including the new entry inthe host 28 having a hash function of the same mechanism as the hashfunction 400, transfer the new VPI/VCI table to the VPI/VCI translator85 and update the VPI/VCI table 402 with the new VPI/VCI table.

Pattern Detector

The host 28 knows what kind of data incoming in over a specific VC. Thehost 28 instruct the patten detector 92, per VC, which pattern is to bescanned for. The purpose of the pattern detector 92 is to detect apreset bit pattern in the incoming data stream. Each time a match isdetected, the pattern detector 92 informs the host 28 the “datadetected” state. When the host 28 receives the information of thedetection, it adds the address at which it occurs to a list in the hostmemory 32. As the detection itself is done automatically, the host 28can perform other jobs in the mean time. The host 28 only needs to beinterrupted in case the pre-set bit pattern is detected and the actioncan be taken.

FIG. 15 shows a block diagram of the pattern detector 92. Before theincoming data stream is transmitted through the reception path 80, thehost 28 instructs the pattern detect controller 506, per VC, whichpattern is to be scanned for. The pattern detect controller 506 can set4 pre-programmed bit pattern of 32 bits wide in register 504 for eachstream. The alignment circuit 500 performs byte alignment of incomingdata stream. The matching circuit 502 performs byte aligned matchingagainst 4 pre-programmed bit patterns per stream. Each time the match isdetected, the matching circuit 502 informs the controller 506 of thedetection.

An example of the purpose of pattern detector 92 is to find locations ofI-picture in video bit stream compressed according to the MPEG standard.In the MPEG bit stream, a picture immediately following GOP header isalways I-picture. Therefore, It is possible to find a location ofI-picture by detecting group_start_code (32 bits) identifying thebeginning of GOP header and picture_start_code (32 bits) identifying thebeginning of picture header.

For instance, when a MPEG bit stream of a movie is transferred fromanother SMU 12 in order to duplicate the movie, group_start_code andpicture_start_code are set in the register 504 as pre-set bit patterns.The pattern detector 92 detects group_start_code and picture_start_codein the received MPEG bit stream. Each time picture_start_code isdetected immediately after the detection of group start code in thematching circuit 502, the pattern detect controller 506 informs thedetection state to the host CPU 30. The host CPU 30 adds an address ofstorage device 20 in which the I-picture is stored to a list in the hostmemory 32. Thus the list indicting locations of I-picture is constructedduring the MPEG bit stream flows in the reception path 80.

The list is used for VCR-operation when the stored MPEG bit stream istransferred to the STB 18. If the STB 18 requests VCR operation (e.g.,FF, FR), the host 28 refers this list and instructs the storage devicecontroller 22 to access and retrieve the I-pictures.

Using this feature, the data stored in the storage device 20 is “raw” ornot formatted for a specific application. This increases the“application independence” and interoperability of server system 10(FIG. 1).

Rx Address Translator

The purpose of the Rx address translator 96 is to gather different(non-contiguous) words from a stream buffer 46 and to create a burstdata to the PCI bus 24. It is basically the inverse function of theaddress translation of the Tx address translator 54. The difference isthat in this case a dynamic buffer structure must be considered. Theburst data is transferred to the storage device 20 or the host 28 viathe PCI bus 24.

FIG. 16 shows an example of an address translation applied to a incomingdata stream to be stored in Disk 0, 1, 2 and 3 of the storage device 20.In this example, the following sequence of read addresses for the streambuffer 48 is generated by the Rx address translator 96 to create a burstdata 600.

178, 182, 13, 17, 1099, 1103 (for Disk 0)

179, 183, 14, 18, 1100, 1104 (for Disk 1)

180, 184, 15, 19, 1101, 1105 (for Disk 2)

181, 185, 16, (for Disk 3)

What is claimed is:
 1. A method for delivering data comprising the stepsof: receiving data from a network; detecting at least first and secondpreset bit patterns in the received data when the received data istransmitted to a storage device; adding location informationcorresponding to locations of said at least first and second preset bitpatterns in the data to a list when said at least first and secondpreset bit patterns are detected; storing the data in the storagedevice; and controlling a delivery of the data from the storage deviceto the network according to the location information of said at leastfirst and second preset bit pattern in the data in the list.
 2. A methodaccording to claim 1, wherein the data includes video data compressedaccording to MPEG standard and the location information represents atleast a location of I-picture, and the step of controlling comprisesaccessing the I-picture of the data stored in the storage deviceaccording to the location information.
 3. A method according to claim 1,wherein detecting at least first and second preset bit patterns includesdetecting the second preset bit pattern immediately following the firstpreset bit pattern.
 4. A methof according to claim 1, wherein the firstpreset bit pattern includes group_start_code in MPEG format.
 5. A methodaccording to claim 1, wherein the second preset bit pattern includespicture_start_code in MPEG format.
 6. An apparatus for delivering datacomprising: receiving means for receiving data from a network; a patterndetector for detecting at least first and second preset bit patterns inthe received data when the data is transmitted from the receiving meansto a storage device; a list for storing location informationcorresponding to locations of said at least first and second preset bitpatterns in the data when said at least first and second preset bitpatterns are detected by the pattern detector; and means for controllinga delivery of the data from the storage device to the network accordingto the location information in the list.
 7. An apparatus according toclaim 6, wherein the data includes video data compressed according toMPEG standard and the location information represents at least alocation of I-picture, and the means for controlling controls thestorage device so that the I-picture is accessed according to thelocation information.
 8. An apparatus according to claim 6, wherein thepattern detector is configured to detect the second present bit patternimmediately following the first preset bit pattern.
 9. An apparatusaccording to claim 6, wherein the first preset bit pattern includesgroup_start_code in MPEG format.
 10. An apparatus according to claim 6,wherein the second preset bit pattern includes picture_start_code inMPEG format.
 11. A method for delivering a video data stream from astorage to receiver devices via a network, comprising the steps of:detecting at least first and second preset bit patterns in the videodata to be delivered; generating location information representing thelocations of the video data corresponding to said detected preset bitpatterns in said video data; and controlling delivery of said video datastream to the network according to the location information of saiddetected preset bit patterns in said video data.
 12. Apparatus fordelivering a video data stream from a storage to receiver devices via anetwork, comprising a processor configured to: detect at least first andsecond preset bit patterns in the video data to be delivered; generatelocation information representing the locations of the video datacorresponding to said detected preset bit patterns in said video data;and control delivery of said video data stream to the network accordingto the location information of said detected preset bit patterns in saidvideo data.